Tile Tracker

Powers off 3V CR2032 lithium coin battery
One piezo buzzer
Toshiba's TC35678FSG BLE 4.2 Cortex-M0 (13 or 26MHz) 384KB ROM, 192KB RAM, 256KB Flash.
Diodes PAM8904 12-pin U-QFN3030-12 18VPP output piezo sounder driver, charge pump
Could not identify the two other ICs

  

FPGA Design on Linux

I'm dusting off an old Digilent Nexys 2 board with a Xilinx Spartan 3E FPGA.  The older FPGA devices are not supported by Xilinx Vivado, and the last version of ISE is 14.7 (2013).  The free webpack license is sufficient.  The Linux install file is about 6.5GB; the installation would take 18GB.   It installs fine except for the cable drivers.  It appears that when trying to build windrvr6.ko kernel module, there is an error "fatal error: linux/config.h: No such file or directory" because Linux does not have config.h.  Because we plan to use Digilent's Adept interface, it is not crucial that we have the Xilinx cable driver.  Instead we install Digilent's adept utility and runtime.

After sourcing Xilinx setup script, we can run ise to start ISE Project Navigator.  Then the graphic interface guides us to create the project and run the implementation and generate the bit file.  Then we use the adept utility djtgcfg to program the FPGA.

Subsequently, it might be easier to run the command line interface.  We can turn the command log into a batch script.

The design can be simulated with ISim Simulator.  Now we have a Xilinx FPGA development environment on Linux.

The Linux version of Microsemi's Libero SoC is also available.  We install Libero SoC v11.9 for the ProASIC3 devices.  But we run into a problem with the license.  We request a free sliver license and install Linux Licensing Daemon.  We run lmgrd to start the license server, but license checkout for synplifypro_actel is unsuccessful: The license key and data for the feature do not match. It turns out that I forget to set the environment variables. That gets the synthesis going. Compile does not work and gives an error message of

"Unable to open a working copy of adb file: checksum error detected. The specified file may not be an Actel design file or may be corrupted."

and another message of

"Wind/U Error (248): Failed to connect to the registry on server Cannot register service: RPC: Unable to receive; errno = Connection refused" .

I tried the suggested solution of allowing TCP connections to Xserver. But it does not work.

Router

I finally retired a ten year old router which can no longer support the speed from the cable modem.  It has been running DD-WRT firmware; now it is time to really hack it.   A router is an embedded computer.  Let's first take a look at the components.  The RF circuitry is in the shielded metal can; we won't get into for now and will look at a later time.  The main SoC is AR9130, Wireless Network Processing Unit (802.11n MAC/Baseband, Fast Ethernet MACs, 2x MIMO, 300Mbps PHY/link rate), 400MHz MIPS32 24K CPU (64KB I-cache, 32KB D-cache), supported by 32MB (16Mx16) 200MHz@CL3 DDR400 SDRAM and 4MB (64x512Kb) 50MHz SPI Flash memory (which does not support QSPI).  AR8216 is a 6-port 10/100 Fast Ethernet switch.  The input power is 5V; there are footprints for input filtering, but are bypassed with zero-Ohm resistors.   The first voltage regulator is a 3.3V synchronous buck at 200KHz with external MOSFETs and a relatively beefy inductor.  There are two LDOs, 2.5V/1.5A and 1.8V/0.6A from 3.3V respectively.  There is another switching regulator that generates 1.2V/1A from 3.3V.  There is one UART serial port through-hole header footprint.  There is also an un-populated USB 2.0 port which is supported by AR9130.   A USB 2 port opens up a lot of possibilities, such as disks, webcam, printer, etc.

OpenWrt is a version Linux for routers.  We'll build a version for this router.  A lot of good information can be found here.  One of the limitations of this router is the 4MB Flash, which we'll upgrade; 16MB version costs only about $2.  It is possible to upgrade SDRAM to 64MB, which is about $4 or possibly to get from old PC DIMM.

We use OpenWrt V17.01.7, which still has direct support in the config for this router.  It uses the buildsystem for LEDE.  It downloads all the sources, patches them and builds both host tools and target systems.  It took over two hours and almost 8GB to build.  It builds some of the common UNIX tools, which seems wasteful but maybe it is the easy way to enforce compatibility.  The toolchain is binutils and GCC as usual.  musl libc is used as the standard C library; it is supposedly lightweight and fast.  It is relatively new, compared to uClibc and newlib.  The host tools and the toolchain do not need to build if the configuration changes; the subsequent rebuild takes about 20 minutes.

By holding the reset button while powering up, it enters the factory firmware upgrade mode.  I tried to load the firmware through browsers without success.  The command line worked,

curl -v --form files=@lede-ar71xx-generic-dir-615-c1-squashfs-factory.bin 192.168.0.1/cgi/index

I could ssh into it.  The version that I built did not have a web interface, which probably is not included by default.  After including uhttpd, luci-mod-admin-full, etc also removing a few packages, such as ppp, ip6tables, etc to keep the image small, we have the web GUI.  We can easily configure the router to bridge the main router.  And firmware upgrade can be done through the web GUI using lede-ar71xx-generic-dir-615-c1-squashfs-sysupgrade.bin .   Note that accessing web interface is not secure; luci-ssl has to be enabled to use https.  The Flash is very close to full; the file system is 2432K and the compressed kernel is 1292K for total about 3724K out of 3776K allocated for the OS.

Reading Computer Architecture

Hennessy and Patterson's Computer Architecture book was first published in 1990 and the sixth edition came out in 2017.  That is a span of almost three decades.  I read a few editions over years since each edition has substantial new materials.  I have gathered every edition.  We will read them again to see how computer architecture has evolved as described by this influential book over 30 years from the 1e 1990, 2e 1996, 3e 2002, 4e 2006, 5e 2011, to 6e 2017 (about 5 years/edition).  [See 7e .]

The 1st edition published in 1990 has over 750 pages with appendices.  The 2nd edition published in 1996 has 1000 pages including the appendices.  The 6th edition has 1500 pages with appendices. 

It would be a mistake not to read the 1st edition (especially for beginner).  (Copies are still available in the used book market for very little cost.)  It lays the foundation for the subsequent editions to follow.  It describes the technology up to 1989.  It describes a hypothetical RISC processor DLX (similar to MIPS).  It emphasizes the importance of making quantitative measurements.  The quantitative principles are actually fairly simple, just some elementary school mathematics.  This seems to make it just an empirical science.  Does the lack of mathematical sophistication mean that the computer architecture discipline is still in its infancy?   The main technical discussions center on pipelining and memory hierarchy, the two fundamental topics that would remain in all editions.  About 100 pages are devoted to the two topics each.  The vector processor and I/O (including storage and network) are also covered.  The DEC VAX and IBM 360 are used as main examples.  In the pre-VLSI days, computer designers seemed to worry a lot about the speed of light being the limiting factor and totally missed the miniaturization brought about by the nanotechnology and the ultimate limitation actually being the power dissipation. 

In the 2e, the graph of microprocessor performance growth shows the top performer DEC Alpha in 1995; the microprocessor performance grows at 1.58x per year (vs 1.35x per year performance growth in technology).  The graph appears to show a SPECint92 rating of 330.  It matches the data from netlib.org: DEC Alpha 21164 266MHz in AlphaStation 600 5/266 of 1995 has a SPECint92 rating of 329.0 and SPECint95 of 6.30.   Intel Pentium 133MHz available at that time has SPECint92 rating of 190.9 and SPECint95 of 3.96.  (A lot of historical CPU performance data can be found at  http://cpudb.stanford.edu/ .)   In the 3e, the top performer is Intel Pentium III of 2000, same growth rate.  Pentium III 1GHz of 2000 has SPECint95 rating of 46.8.  In the 4e, the top performer is Intel Xeon 3.6GHz; the growth rate is revised to show 25%/year before 1986, 52%/year 1986-2002 and 20% 2002-2005.  In the 5e, the top performer is Intel Xeon 6 cores 3.3 GHz; the growth rate after 2003 is 22%/year.  In the 6e, the top microprocessor is Intel Core i7 4 cores 4.2GHz; the growth rate after 2003 is refined: 23%/year 2003-2011, 12%/year 2011-2015, 3.5%/year 2015-2017.

Also notable is the scaling of clock rate:  the first 15 years (1987-2003), the clock rate goes from 16MHz to 3.2GHz (40%/year increase), and the recent 15 years (2003-2017) the clock rate goes from 3.2GHz to 4.2GHz (2%/year).  Between 2003 and 2010, there was almost no improvement in clock rate.  FinFET technology production (22nm) started around 2011, which possibly boosted clock rate slightly.  The power limitation is first mentioned in the 3e as power consumption reaches over 100W.  (Xeon 9282 launched in 2019Q2 reaches TDP of 400W.) 

The 2e emphasis is mostly on the RISC principle; one entire chapter is devoted to describe the RISC instruction set, which DLX is still used as a textbook example.  The DLX instruction set is simple by using load-store, fixed encoding, and large register set.  The question about CISC vs RISC is settled decisively by comparing CPI (cycles per instruction) and number of instructions executed using the quantitative principles. RISC's CPI advantage more than compensating for the more instructions per program and RISC is much simpler to build.  Rarely used complex instructions just do not pay off.  ILP (instruction-level parallelism) is the main focus from basic pipelining, dynamic scheduling, branch prediction, superscalar, speculation to compiler technology.  The fundamental ideas remain unchanged through editions.  The modern superscalar speculative dynamic processor has gotten very complex.  It is hinted that multiprocessor may be the way to go as it is possible to put two processors on a single die around the end of the 20th century.  The chapter on the vector processors is moved to the appendix.  The storage systems and networks are are discussed.

TLP (thread-level parallelism) first appears in 3e.  Basic pipelining is relegated to the appendix. DLX is replaced by MIPS as an example for instruction set principle.

From 4e, instruction set principles and networks are relegated to the appendix.  No major new topic is introduced in this edition.

DLP (data-level parallelism) is first introduced in 5e.  GPU is first described as DLP.  The vector processor finally makes a comeback into the DLP section; it is included in the appendix of the previous 3 editions.  RLP (request-level parallelism) is also introduced.  WSC (warehouse-scale computers) is coined; WSC is made of hundred thousands of networked servers.  

DSA (domain-specific architecture) is first discussed in 6e; the AI neural chips are presented as the examples.  RISC-V is used as an example for instruction set principle.

$3 USB Li+ Battery Charger

The $3 Li+ battery charger is very simple in construction.  It has a single layer PCB.  I could not identify the IC, which linearly regulates the voltage and the current from the USB 5V input.   It also controls two LEDs, so it may be designed for this application.  One 2K resistor is possibly for programming the current. It draws about 5mA when idle and 500mA when charging.  It cuts off at the right voltage of 4.2V.  But the open circuit voltage is 4.38V.  The negative battery terminal tab is spring loaded to accommodate different battery sizes.

LoRa on RPi

LoRa is a low-power and long distance wireless technology.  I have a set of Semetch SX1272 boards.  We'll try to use them to communicate between two Raspberry Pi boards (Pi3 and Pi4).

Wire the 4 SPI signals to the header, and add a GPIO for reset.  I also wire up an LED.  First checkout the connection by reading the "RegVersion" register at address 0x42 and expect a value of 0x22.  The chip operates in Mode 0 (CPOL=0, CPHA=0).

import spidev
spi=spidev.SpiDev(0,0)
spi.max_speed_hz=1000000
spi.xfer([0x42,0]) 

It returns [0, 34].  Note that the SPI max speed depends on the wiring.

There are a few Python modules that support SX1272.  We'll try to make use of Adafruit's Python package for RFM9x, which is said to use SX1272 (although the IC has its own marking).  The first attempt to use adafruit_rfm9x was unsuccessful; it could not find the device.  It appears that RFM9x uses an older version of the chip and there is some additional circuitry on the module Furthermore, the CircuitPython implementation of the SPI device interface for RPi seems a little convoluted.  It fails at the very beginning trying to read the version register.

We move on to use raspi-lora for RFM9x.  It requires only RPi.GPIO and spidev.  One GPIO input is needed as interrupt for receiving.  The code is simple.  It worked on the first try; messages sent from RPi3 were received by RPi4.

Another Python package python-sx127x also works.

PSoC Development on Linux

PSoC from Cypress is a unique microcontroller for the flexibility of its peripherals.  The low-cost PSoC 5LP prototyping kit CY8CKIT-059 is particularly attractive with $10 price and built-in programmer and debugger KitProg.  The PSoC5 series has an ARM Cortex-M3 core, which is supported by the GNU compiler.  However, the develop environment Cypress PSoC Creator only runs on Windows.  My attempt to run PSoC Creator with Wine was unsuccessful.  I can run PSoC Creator on Windows virtual machine, in which the peripherals can be set up.  (The last version supported on Windows XP is 4.0 (Release Date 10/06/2016).) Once the hardware configuration is generated, the software development can be done in Linux.

One way to update the application software on Linux is to use a bootloader.  Cypress supplies a bootloader component, that can communicate over UART, I2C, and USB HID.

First we have to flash the bootloader itself; we can use OpenOCD, which has support for KitProg.   The Linux kernel detect KitProg (ID 04b4:f139) as a USB HID device and a serial port.

[ 1995.852252] usb 1-1.2.2: new full-speed USB device number 11 using ehci-pci
[ 1995.968208] usb 1-1.2.2: New USB device found, idVendor=04b4, idProduct=f139, bcdDevice= 2.11
[ 1995.968217] usb 1-1.2.2: New USB device strings: Mfr=1, Product=2, SerialNumber=128
[ 1995.968222] usb 1-1.2.2: Product: Cypress KitProg
[ 1995.968227] usb 1-1.2.2: Manufacturer: Cypress Semiconductor
[ 1995.968231] usb 1-1.2.2: SerialNumber: 1016163201324400
[ 1995.970949] hid-generic 0003:04B4:F139.0003: hiddev0,hidraw1: USB HID v1.11 Device [Cypress Semiconductor Cypress KitProg] on usb-0000:00:1a.0-1.2.2/input0
[ 1996.015524] cdc_acm 1-1.2.2:1.2: ttyACM0: USB ACM device
[ 1996.017170] usbcore: registered new interface driver cdc_acm
[ 1996.017172] cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters

After building openocd from the source, openocd detects KitProg,

./src/openocd -s ./tcl/ -c "interface kitprog" -f target/psoc5lp.cfg -c "targets"
Open On-Chip Debugger 0.10.0+dev-g9a363c9 (2020-02-09-14:02)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'swd'
cortex_m reset_config sysresetreq
    TargetName         Type       Endian TapName            State       
--  ------------------ ---------- ------ ------------------ ------------
 0* psoc5lp.cpu        cortex_m   little psoc5lp.cpu        unknown
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : KitProg v2.17
Info : Hardware version: 17
Info : VTARG = 4.755 V
Info : This adapter doesn't support configurable speed
Info : SWD DPIDR 0x2ba01477
Info : psoc5lp.cpu: hardware has 6 breakpoints, 4 watchpoints
Info : Listening on port 3333 for gdb connections
Info : accepting 'telnet' connection on tcp/4444

To program the bootloader, 

../Cypress-OpenOCD/src/openocd -s ../Cypress-OpenOCD/tcl/ -c "interface kitprog; kitprog_init_acquire_psoc" -f target/psoc5lp.cfg -c "init; halt; program output/debug/Bootloader_USBUART.elf  verify reset exit"
Open On-Chip Debugger 0.10.0+dev-g9a363c9 (2020-02-09-14:02)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'swd'
cortex_m reset_config sysresetreq
Info : KitProg v2.17
Info : Hardware version: 17
Info : VTARG = 4.758 V
Info : This adapter doesn't support configurable speed
Info : SWD DPIDR 0x2ba01477
Info : psoc5lp.cpu: hardware has 6 breakpoints, 4 watchpoints
Info : psoc5lp.cpu: external reset detected
Info : Listening on port 3333 for gdb connections
target halted due to debug-request, current mode: Thread 
xPSR: 0x41000000 pc: 0x000004b8 msp: 0x20007fc8
target halted due to debug-request, current mode: Thread 
xPSR: 0x01000000 pc: 0x00000010 msp: 0x20008000
** Programming Started **
auto erase enabled
Info : Padding image section 0 at 0x00001869 with 3 bytes
Info : Flash write discontinued at 0x00001de0, next section at 0x0003ffc0
Warn : Adding extra erase range, 0x0003c000 .. 0x0003ffbf
Error: Writes must be row-aligned, got offset 0x0003ffc0
Error: error writing to flash at address 0x00000000 at offset 0x0003ffc0
** Programming Failed **
shutdown command invoked
Error: Sequence 2 not supported.

If the hex file is used, the error message is different,

** Programming Started **
auto erase enabled
Warn : no flash bank found for address 0x80000000
Warn : There is no erase operation for NV Latches
Error: failed erasing sectors 0 to 0
** Programming Failed **
shutdown command invoked
Error: Sequence 2 not supported.

 Despite of the error message, the programming of the bootloader seems to have succeeded.

The UART bootloader works with a Linux version of bootloader_host, cyhostboot, built around the source for Bootloader Host Tool provided by Cypress, available on Github.

../cypress_linux_tools/cyhostboot/cyhostboot -f output/debug/PSoC5ino.cyacd
Programing file output/debug/PSoC5ino.cyacd
Start programing on serial /dev/ttyACM0, baudrate 115200
no parity
Got silicon id 0x2e161069, rev 0x00
Progress: array_id 0, row_num 30
Progress: array_id 0, row_num 31

... 

Progress: array_id 0, row_num 149
Progress: array_id 3, row_num 255
programing OK !

It takes about 2 minutes to program about 30KB.