PCB layout: Techniques

Two-layer Board

Two-layer boards are the most common for low-cost applications. The PCB vendors normally offer 6mil minimum trace width and trace separation and 14mil minimum hole size. Some offer boards without solder masks at very attractive prices. Because of the lack of dedicated power and ground planes, the quality of the layout is largely determined how to manage power and ground traces. And the effective use of copper area for ground can reduce noise coupling and EMI. Good layout software will help a great deal; time spent on learning to use the tools is worthwhile. Knowing the keyboard shortcuts will improve efficiency. The following discussion assumes features supported by Protel or Orcad.

Setup

The first thing is to set up rules for trace width and clearance. Set minimum width and clearance higher than the fab house minimum. It improves board durability and reduces fab related issues. Set nominal (or preferred) width larger than the minimum and power and ground traces should have larger nominal width, but allow smaller width so they can be connected to pads. Then select a default via size. Make sure to specify an adequate annular ring size, usually at least the minimum trace width. I prefer to have solder mask over vias (tented vias). Some layout software let you specify the solder mask expansion, usually 3-4mils. The thermal relief should also be specified. The layout process is error-prone; make the computer do the check. The next thing is to set up the board outline and as well as the keep out area. The traces/holes should not be too close to the edge, say 50mil from the edge.

Placement

A good layout is predicated on a good placement. The placement grid makes easier to align certain components. Set an appropriate grid size based on the packages; 20mil is probably a good choice for placement and 10mil for routing. Choosing a different rats nest color for power nets can be helpful. Components can usually be grouped logically, such as power, analog, digital, RF etc. Be careful not to mix noisy digital signals with sensitive analog signals. High current sections should be closer to the power regulator to minimize noise. In the first pass, bring in the related components proximity. Cross-probing with schematics is useful here. There are usually some constraints on some components, such as mounting holes, connectors etc. Place these first and lock their locations. The other components locations and orientations are adjusted to minimize trace lengths to other connected components. Here some experiences come in to judge the ease of layout later. Consider the critical nets first; ensure that they have direct and short paths. It takes some trial and error; move components around until the distribution of nets seems even and not clustered together. Look at the density map if the software produces it. If certain areas appear congested, increase room that allows more traces to route. Place fiducial marks. Do a design rule check before moving on. The placement in the end should also be aesthetically pleasing.

Routing

Route the critical nets first. Then route the power and ground. Route analog nets and high speed nets before others. Do not worry too much about getting all traces neat and tidy first. Clean up later. In general, orient the trace in one direction on the top layer and in the orthogonal direction on the bottom layer. The goal is to minimize trace length and number of vias. Once all traces are routed, examine the nets again to optimize: straighten out traces, widen power and ground traces, reroutes traces to remove vias, etc. In the end, create copper pour for ground and power. Make small adjustments for maximum continuous copper area. The ability to turn on and off copper area would be helpful. Add teardrop if the tool supports it.

Verification

Check routing statistics to make all traces enabled and routed. Run DRC and resolve any issues. Silk screen labels orientation should be consistent. Include pin 1 and polarization marking. Leave a silk screen area for labeling. Add necessary labels, such as jumper settings. Make sure no silk screen over pads; I wish there is a design rule for that. Move silk screen labels away from via holes, which make silk screen labels illegible. Look at individual layers by itself, especially the solder mask to ensure the pads are exposed. Look at layers in the outline mode. If the software can generate 3D view, take a look to see if board looks correct.

Output

The last step is to generate the CAM files, usually Gerber files. Load Gerber files into a Gerber viewer. Look at the bottom layer from the bottom side. Also produce drawing files in format such as PDF. Generate composite top and bottom view, drill drawing with drill tables. Print out a copy and look at it. When designing a board that plugs into another board, it is helpful to print the layout on a transparency and do a fit check again the other board to make sure connectors and holes line up correctly.