Multi-Slope ADC on PSoC5

High-resolution multimeters use multi-slope ADC to digitize analog voltages.  Here we implement a multi-slope ADC on a PSoC5 device; all the circuitries are inside the PSoC except for a capacitor and resistors.  The design is based on the description given in AoE3.

The bandgap reference provided is 1.024V (+/- 0.5%); it is measured 1.019V, or 0.5% from the nominal, just within the spec.   This reference is doubled to be the upper reference  and the ground is the lower reference; so the ADC range is [0, 2.048] V.   The upper reference is measured to be 2.060V; the PGA gain error can be +/-4%.  The circuit switches between the upper and lower reference to keep the integrator output near 1.024V.  One counter counts up and down according to the switch position.  At the end of the conversion, the counter value is captured and  a 12-bit SAR ADC measures the residue.  The combination is the multi-slope ADC output.

We test it by stepping the input from 0 to 2.5V in 0.1V step and convert only counts to voltages.  We get the following results.  The step size appears correct, but there is 0.1V offset, which we'll look into.