ChipQuik
The normal solder (63% Sn 37% Pb) has a melting temperature of 361F (183C). ChipQuik has a very low temperature solder (48% Sn 28%Pb 21%In 3%Bi) which has a melting temperature of 136F(58C). When ChipQuik solder combines with the regular solder, the new alloy has a melting temperature of 150F. So surface mount devices can be removed with the ChipQuick solder by keeping the solder molten with only 150F (low enough not to damage the devices).
Monday, April 2, 2012
Monday, March 26, 2012
EE Notes
Motor winding insulation temperature ratings
NEMA classes are A (105C), B (130C), F (155C), H (180C). Class B is the most prevalent since 1960's.
SLA Battery Charging
Current limited (0.25C) charge to 2.45V/cell then drop to 2.30V/cell.
LiFePO4 Battery Charging
Current limited (0.2C - 0.7C) charge to 3.65V/cell hold till the current drops to 10% of initial charge rate.
Chip Resistors
0402 resistors are most commonly 1/16W.
0603 resistors are most commonly 1/10W.
0805 resistors are most commonly 1/8W.
1206 resistors are most commonly 1/4W.
Tantalum Capacitors
The voltage ratings are usually 50V or below. Even at 50V, the large value tantalum capacitors are expensive, so Aluminum electrolytic should be considered instead.
Relay
1-Form-A: single pole normally open
1-Form-B: single pole normally closed
1-Form-C: single pole double throw
NEMA classes are A (105C), B (130C), F (155C), H (180C). Class B is the most prevalent since 1960's.
SLA Battery Charging
Current limited (0.25C) charge to 2.45V/cell then drop to 2.30V/cell.
LiFePO4 Battery Charging
Current limited (0.2C - 0.7C) charge to 3.65V/cell hold till the current drops to 10% of initial charge rate.
Chip Resistors
0402 resistors are most commonly 1/16W.
0603 resistors are most commonly 1/10W.
0805 resistors are most commonly 1/8W.
1206 resistors are most commonly 1/4W.
Tantalum Capacitors
The voltage ratings are usually 50V or below. Even at 50V, the large value tantalum capacitors are expensive, so Aluminum electrolytic should be considered instead.
Relay
1-Form-A: single pole normally open
1-Form-B: single pole normally closed
1-Form-C: single pole double throw
Sunday, March 4, 2012
EEssential Weekly Notes #5
Ferrite bead vs Inductor
The ferrite bead is lossy at high frequencies, i.e. low Q or resistive. The high frequency energy are absorbed and dissipated as heat. A pure inductor is non-lossy and stores energy. While a real inductor has some inevitable resistive element, it absorbs energy equally at all frequencies.
Mu-Metal
Mu-metal is high permeability material; it achieves the magnetic field shielding by redirecting magnetic field lines.
The ferrite bead is lossy at high frequencies, i.e. low Q or resistive. The high frequency energy are absorbed and dissipated as heat. A pure inductor is non-lossy and stores energy. While a real inductor has some inevitable resistive element, it absorbs energy equally at all frequencies.
Mu-Metal
Mu-metal is high permeability material; it achieves the magnetic field shielding by redirecting magnetic field lines.
Sunday, February 12, 2012
PCB Layout: Basics
PCB layout generally is not a task that many EE's are proficient at. They may even consider it somewhat beneath them and it is the work for technicians. Many schools do not consider it significant enough to warrant a course and EE students are expected to pick it up by themselves when needed. But actually PCB layout concerns a wide range of topics, including material science, electrical engineering, mechanical engineering, thermal engineering, packaging technology, fabrication technology, assembly etc. A good layout engineer must be aware of concepts in all these areas.
Let's start with printed circuit board materials. The basic conducting material is copper, an excellent conductor of both electricity and heat. The thickness of copper is given in ounce, the weight of one square foot; one ounce and two ounces are common. The thickness of 1oz copper is given as 1.37mil. (The copper density is 8.96g/cm3, so 1.37mil is 1.02oz.) Exposed copper traces are usually coated with very thin layer of tin or nickel (~0.1mil) for preventing oxidation. Outer layers and via are plated with copper. Electrical resistivity with temperature coefficient and thermal conductivity are relevant to PC layout. Plated copper has higher resistivity than copper sheet. The most common PCB dielectric is FR4, others include G10, polyimide. Dielectric constant with frequency variation and loss tangent are needed for layout. The temperature range where the dielectric is stable is also important. Polyimide has higher temperature range than FR4, so it is used in space electronics. PC boards are built in layers with core and prepreg. Prepreg bonds core laminates under pressure and temperature. Board is covered with solder mask except for pads or other exposed areas. The solder mask gives the PCB the common green color, but the other colors are also available, such as blue, maroon and white. Silkscreen is used for component labels.
From electrical point view, PCB traces establish electrical connectivities, but they add resistance, inductance and capacitance. Resistance causes joule heating and voltage drops. Especially for high current traces, trace width must be sized correctly. Charts are given in current vs trace width for different temperature rise. Note that outer layer traces can carry much larger current for the same temperature rise. Trace inductance and capacitance are more important in high speed designs, where they may significantly impact signal integrity. Electromagnetism which has been simplified to Kirchoff laws in circuit design now manifest itself in its full form. The spatial arrangement becomes important. EM compliance has to be dealt with in layout. Transmission line effect has to be taken into account. 2D and 3D field solvers are becoming more routinely employed to determine signal integrity in high speed applications.
PCB is after all a mechanical structure. It has to be mechanically mounted to other structures. Design files convey mechanical information. Some terminologies come from mechanical engineering.
PCB is also a medium for heat to conduct. Thermal analysis of circuit board depend on the layout. Layers can be added for thermal purpose, copper area can be created to reduce thermal resistance.
Circuit elements come in various of packages. A layout engineer must keep abreast of advances in packaging technologies.
PCB layout is bounded by the capabilities of fabrication technologies and cost. A layout engineer must be aware of constraints placed by these capabilities and aim for reliable manufacturing. 7 mil minimum trace width and spacing are fairly routine.
During actual layout, component placement is the most important for it eventually determines the qualities of layout. A proper partition of the circuit section is guided by the foremost by the current flow. The loop area must be minimized. High current circuit sections should be close to the voltage source and away from the sensitive circuits.
Layout is prone to human errors. Long gone are the days when layout is done manually with tape. A good layout software is essential.
Continued here.
Let's start with printed circuit board materials. The basic conducting material is copper, an excellent conductor of both electricity and heat. The thickness of copper is given in ounce, the weight of one square foot; one ounce and two ounces are common. The thickness of 1oz copper is given as 1.37mil. (The copper density is 8.96g/cm3, so 1.37mil is 1.02oz.) Exposed copper traces are usually coated with very thin layer of tin or nickel (~0.1mil) for preventing oxidation. Outer layers and via are plated with copper. Electrical resistivity with temperature coefficient and thermal conductivity are relevant to PC layout. Plated copper has higher resistivity than copper sheet. The most common PCB dielectric is FR4, others include G10, polyimide. Dielectric constant with frequency variation and loss tangent are needed for layout. The temperature range where the dielectric is stable is also important. Polyimide has higher temperature range than FR4, so it is used in space electronics. PC boards are built in layers with core and prepreg. Prepreg bonds core laminates under pressure and temperature. Board is covered with solder mask except for pads or other exposed areas. The solder mask gives the PCB the common green color, but the other colors are also available, such as blue, maroon and white. Silkscreen is used for component labels.
From electrical point view, PCB traces establish electrical connectivities, but they add resistance, inductance and capacitance. Resistance causes joule heating and voltage drops. Especially for high current traces, trace width must be sized correctly. Charts are given in current vs trace width for different temperature rise. Note that outer layer traces can carry much larger current for the same temperature rise. Trace inductance and capacitance are more important in high speed designs, where they may significantly impact signal integrity. Electromagnetism which has been simplified to Kirchoff laws in circuit design now manifest itself in its full form. The spatial arrangement becomes important. EM compliance has to be dealt with in layout. Transmission line effect has to be taken into account. 2D and 3D field solvers are becoming more routinely employed to determine signal integrity in high speed applications.
PCB is after all a mechanical structure. It has to be mechanically mounted to other structures. Design files convey mechanical information. Some terminologies come from mechanical engineering.
PCB is also a medium for heat to conduct. Thermal analysis of circuit board depend on the layout. Layers can be added for thermal purpose, copper area can be created to reduce thermal resistance.
Circuit elements come in various of packages. A layout engineer must keep abreast of advances in packaging technologies.
PCB layout is bounded by the capabilities of fabrication technologies and cost. A layout engineer must be aware of constraints placed by these capabilities and aim for reliable manufacturing. 7 mil minimum trace width and spacing are fairly routine.
During actual layout, component placement is the most important for it eventually determines the qualities of layout. A proper partition of the circuit section is guided by the foremost by the current flow. The loop area must be minimized. High current circuit sections should be close to the voltage source and away from the sensitive circuits.
Layout is prone to human errors. Long gone are the days when layout is done manually with tape. A good layout software is essential.
Continued here.
Thursday, February 2, 2012
EEssential Weekly Notes #4
Bond wires
The standard bondwire is 1mil in diameter and 2mm in length. It has very roughly 1nH/mm. [T. Lee, CMOS RF] A D-PAK MOSFET (AOD452) has 6.5mOhms Rds on with 2x12mils wire bond; the wire resistance is ~0.6mOhm. [Alpha & Omega, AN911]. The package resistance is about 20% of total MOSFET resistance. For DPAK, the package resistance is 0.5mOhm with Powerbond II [Infineon, PowerBond].
Flex circuits
For Minco, 16 layers max, 1.5mil min trace/space, 2mil min hole diameter, 6mil thick per layer.
Solder Conductivity
The 63% tin 37% lead solder alloy electric resistivity is 144e-9 Ohm-m, thermal conductivity 40.9 W/m-K, and thermal expansion coefficient 21.4e-6/C. As a comparison, the copper resistivity is 17e-9 Ohm-m. So the solder has more than eight times the resistance. Plugging a via hole with solder would do very little to reduce its resistance.
The standard bondwire is 1mil in diameter and 2mm in length. It has very roughly 1nH/mm. [T. Lee, CMOS RF] A D-PAK MOSFET (AOD452) has 6.5mOhms Rds on with 2x12mils wire bond; the wire resistance is ~0.6mOhm. [Alpha & Omega, AN911]. The package resistance is about 20% of total MOSFET resistance. For DPAK, the package resistance is 0.5mOhm with Powerbond II [Infineon, PowerBond].
Flex circuits
For Minco, 16 layers max, 1.5mil min trace/space, 2mil min hole diameter, 6mil thick per layer.
Solder Conductivity
The 63% tin 37% lead solder alloy electric resistivity is 144e-9 Ohm-m, thermal conductivity 40.9 W/m-K, and thermal expansion coefficient 21.4e-6/C. As a comparison, the copper resistivity is 17e-9 Ohm-m. So the solder has more than eight times the resistance. Plugging a via hole with solder would do very little to reduce its resistance.
Sunday, January 29, 2012
Hierarchical Design in Altium
Altium Designer promotes hierarchical design, which seems to make sense. It can help manage large designs and encourage design reuse. Those concepts have long been prevalent in software design. In a true hierarchical design, the local nets should stay local, but Altium seems to have problems with sheets with same named local nets. We are forced to define unique names to different sheets.
The ports are considered differently from the wires; so the port names do not become signal names even when the wires are not named. This may be a little unexpected. If we think of ports are module interface declaration, inside the module, the port name should be used as signal names. More confusion is created when the nets are flatten: what net names are ultimately used if nets are assigned names in the hierarchy. Altium would even complain about same net names in different hierarchy. There does not seem to have a well defined way of resolving net names.
Another thing that could cause confusion is the netlist option "Allow Ports to Name Nets". If we try to connect nets by name, we find Altium actually consider the net with net label and the net connect to the port with the same name to be different in PCB while showing exactly the same name. The rule for flattening the netlist seems applied inconsistently. For some nets, the net labels are used and for other the port names are used in the final PCB netlist even though both net labels and port names are assigned.
Altium cannot use a multi-part component in the multiple instances. A hex inverter IC has six inverters. If one is used in a sheet and the sheet is used in multiple instances, Altium will end up with multiple ICs rather than distribute subparts to different instances. But there is not an easy way to resolve this.
In conclusion, the hierarchical design in Altium has to applied with greater caution. I do find some utility for it when a design block are used more than once, but otherwise it is better to avoid at this moment
The ports are considered differently from the wires; so the port names do not become signal names even when the wires are not named. This may be a little unexpected. If we think of ports are module interface declaration, inside the module, the port name should be used as signal names. More confusion is created when the nets are flatten: what net names are ultimately used if nets are assigned names in the hierarchy. Altium would even complain about same net names in different hierarchy. There does not seem to have a well defined way of resolving net names.
Another thing that could cause confusion is the netlist option "Allow Ports to Name Nets". If we try to connect nets by name, we find Altium actually consider the net with net label and the net connect to the port with the same name to be different in PCB while showing exactly the same name. The rule for flattening the netlist seems applied inconsistently. For some nets, the net labels are used and for other the port names are used in the final PCB netlist even though both net labels and port names are assigned.
Altium cannot use a multi-part component in the multiple instances. A hex inverter IC has six inverters. If one is used in a sheet and the sheet is used in multiple instances, Altium will end up with multiple ICs rather than distribute subparts to different instances. But there is not an easy way to resolve this.
In conclusion, the hierarchical design in Altium has to applied with greater caution. I do find some utility for it when a design block are used more than once, but otherwise it is better to avoid at this moment
Monday, January 23, 2012
EEssential Weekly Notes #3
Backdrilling
Backdrilling is a PCB design technique to remove stub from a through-hole. It is to reduce reflection from the stub for the high-speed signals (>5Gb/s). Blind vias and buried vias can achieve the same effect for vias, but at a increased manufacturing cost. But backdrilling is especially useful for backplane connectors, but seems only applicable for press-fit connectors.
Backdrilling is a PCB design technique to remove stub from a through-hole. It is to reduce reflection from the stub for the high-speed signals (>5Gb/s). Blind vias and buried vias can achieve the same effect for vias, but at a increased manufacturing cost. But backdrilling is especially useful for backplane connectors, but seems only applicable for press-fit connectors.
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