80486 PC: CPU

I just recently opened a box of parts from my first PC.  It was purchased in 1994 from a computer store in Pasadena for maybe $1,800.  Back then, there were numerous computer stores that assembled and sold PCs, Microsoft was still a year away from releasing Windows 95 and Linux was just starting to gain a following.  I decide to resurrect this old PC, and provide a very detailed description of this PC.  I'll try to include as much information as I can possibly gather. I think it'll be interesting to review this 20 years old technology and draw some comparison with the current technology.

CPU

Intel 80486DX2 was fabricated on 5V 0.8u (or 800nm in today's unit) process and contains 1.2 million transistors.  It was first introduced in March 1992.  By 1994, Pentium which has 3 times as many transistors had already appeared, so 486DX2 was probably sold at reasonable price.  The 0.8u was already a mature process; the leading edge process was 0.6u.

The 4th generation x86 processor was first introduced in April 1989.  While the instruction set is similar to the 386 with addition of only six new instructions, it integrates on-chip the floating number processor and unified L1 cache.  i486DX2 has 8KB write-through cache. The processor runs at 66MHz and the front side bus is at half speed of 33MHz.  While software compatible with 386, the processor bus is not.  Intel literature said i486 featured a 32-bit RISC-technology core despite of x86 carrying CISC baggage; so by then it is clear RISC is preferred computer architecture.

i486DX2 comes in 17x17 168-pin 0.1" pitch PGA ceramic package, which was quite common for that era.  The PGA packaging would continue except for Pentium II which used the slot package.  Eventually, land grid array, LGA, a surface mount technology would become the standard.  Throughout ZIF sockets are used to house the CPUs.  The maximum power for i486DX2 is about 6W.  The junction-ambient thermal resistance is 17 deg/W.  A heat sink with forced air flow would be required to operate at room temperature. 

Twenty years later, the transistor count is increased by three orders of magnitude, the clock frequency by a factor of 50, the power consumption by 20, the pin count by 10 and the core voltage dropped by 5.

i486 features a five-stage pipeline, so many instructions execute in one clock cycle.  The design goal was to have 2 to 3 times performance improvement over 386 at the same clock with 4 times the transistor budget.  Intel made extensive use of CAD tools developed in cooperation with UC Berkeley.   Intel created its own hardware description language, iHDL, which was not replaced by Verilog until 2005.  Standard cell library was created to enable automatic RTL to layout conversion.  It was first time RTL to layout system ever employed in a major microprocessor development program, though it is only applied to the control logic.  Data path was still done manually.  It is interesting to note that Intel had been using transparent latches with a two-phase clocking system, which was not compatible with synthesis tools.  By the time of Pentium design, the two-phase clocking scheme was largely replaced by a single-clock and master-slave flip-flops. [Gelsinger, "Coping with the Complexity of Microprocessor Design at Intel –  A CAD History"]

The main enhancement of 486 over the previous generation is the inclusion of 8KB on-chip cache, which is a buffered write-through four-way set-associative with LRU replacement 16-byte line size. [Crawford, "The i486 CPU: Executing Instructions in One Clock Cycle", Feb. 1990]  About a quarter of the die area is occupied by the cache.  Today's core would have 32KB data and 32KB instruction L1 cache and an internal unified L2 cache of 256KB and multicore processor could have more than 20MB L3 cache shared by all cores on chip.  The L1 instruction cache is 4-way associative and the data cache 8-way associative; the L2 cache is 8-way associative and the L3 cache 16-way associative.  And the cache would take up majority of the die area.

i486DX2 has 32-bit address lines with byte enable signals, 32-bit data lines with parity, write/read memory and I/O control, bus control, bus arbitration, burst control, cache control signals.  Out of the 168 pins, 24 are Vcc and 28 are Vss.  JTAG boundary scan ports are included.  The CLK input has a maximum frequency of 33MHz.  The logic input level is TTL compatible, i.e. 2.0V and above as high.  The minimum setup time is 5ns, and hold time 3ns.

Slow Decay or Fast Decay

When driving PWM to a motor with an H-bridge, we face with the choice of how to drive the off state.  The options are tri-stating the drivers and shorting the output.  If the drivers are tri-stated, the inductance of the motor forces the current to flow through the body diodes from the lower FET of a leg to the upper FET of the other leg, so effectively the bus voltage minus two diode drops is appled to the motor.  The current decays fast.   The current flows back to the source, captured by capacitors.  If the low FET is left on for the off-state, effectively shorting the motor terminals, the current recirculates and the current decays slowly and dissipates in the motor resistance.   So the torque would be smoother with the slow decay. 

If synchronous rectification is used, the things can get a little more complex.   If the current has completely decayed and the FETs are still on, the motor goes into the generator mode and the motor terminals are shorted, so the motor is braking.

74LS series on 3.3V

The good old 74LS series, once the staple of logic design, is all but forgotten, except that there might still be a lot lying around.  These parts are only specified at 5V +/-5%.  Can they run on 3.3V supply?    When they run on 5V supply, their output is about 3.6V which is safe for the 3.3V logic.  And they can still operate at 3.3V, the output is about 2V, which is still acceptable for 3.3V logic.  Their inputs are 5V tolerant.

Vias: to tent or not to tent

A question sometimes comes up concerning whether to tent or not tent the vias on a PCB.  Altium by default does not tent the vias.  There are several considerations.  The silkscreen can be visible over the tented vias.  The bare vias can be used as test points and for reworks.  The fanout vias for the BGA pads must be tented, otherwise shorts could happen.  If a via is very close to the SMT pad, it is better to tent otherwise it is harder to solder.  A large via cannot be tented completely.   If only one side is tented, it could trap flux and cleaning fluids. Then there is the subtle question about outgassing: a tented via might outgas.

Fuses in Parallel

Occasionally, we may need fuses in parallel to achieve greater current rating.  For instance, the Mini ATO fuses come maximum 30A; any more than that, two or more fuses are needed.  So are parallel fuses advisable?  Yes, it is better to stick with fuses of the same type and rating.   The current will not distribute precisely equally among the fuses.   But they will not differ two much before the self-balance nature of the fuse resistance.  The circuitry should be as identical as possible.  One company recommends, as a general rule, a minimum reduction in rated current of  10% for 2 fuses in parallel (20% for 3 or 4 fuses in parallel).

Velocity Control

Consider the simplest case, a body is acted on only by the force that you control.  You want to reach certain speed; how should you control the force.  If we elect to use the proportion gain control, i.e. the force is proportion to the difference between the desired speed and the current speed.  We would have an exponential speed profile, that approaches the desired speed asymptotically with a time constant of m/K, which m is the mass and K is the proportional constant.

If there is a constant force also acting on the body, such as the gravity, and we apply the proportional control, the speed profile is again an exponential with the same time constant.  But now our final asymptotic speed is not the desired speed, but offseted by mg/K.  So the proportional control results in a steady state error.

The common cure is to add another force that is proportional to the accumulated or integrated velocity error.  Now we have a second order system.   If the integrated gain is sufficiently high,  we would have an oscillatory response.

Motor winding current and supply current

When the motor drive operates in the torque mode, a constant torque implies a constant current in the motor winding.  But we see the supply current varies as the motor speed changes.  The supply current is at the lowest when the motor stalls and the highest when the motor moves the fastest.  The total energy provided by a constant voltage source is consumed by the winding resistive loss and the work done by the motor.  When the armature current is constant, the resistive loss is constant.   The work done by the motor is the torque multiplied by the motor speed.

How does the motor drive keep the winding current constant when the supply varies?  When the load is greater than the motor torque, the motor slows down and stalls.  If the drive keeps the same PWM on period, the current would increase; so the PWM duty cycle is reduced to keep the current constant by the current loop.  The PWM duty cycle is proportional to the motor speed (assume the winding resistance is small).  The drive circuit draws current from the supply during the on period of the PWM cycle.  The peak current is same if the constant winding current is maintained.  So the average supply current is smaller when the motor speed is reduced.

Therefore to infer winding current from the supply current, the PWM duty cycle has to be known.