80486 PC: CPU

I just recently opened a box of parts from my first PC.  It was purchased in 1994 from a computer store in Pasadena for maybe $1,800.  Back then, there were numerous computer stores that assembled and sold PCs, Microsoft was still a year away from releasing Windows 95 and Linux was just starting to gain a following.  I decide to resurrect this old PC, and provide a very detailed description of this PC.  I'll try to include as much information as I can possibly gather. I think it'll be interesting to review this 20 years old technology and draw some comparison with the current technology.

CPU

Intel 80486DX2 was fabricated on 5V 0.8u (or 800nm in today's unit) process and contains 1.2 million transistors.  It was first introduced in March 1992.  By 1994, Pentium which has 3 times as many transistors had already appeared, so 486DX2 was probably sold at reasonable price.  The 0.8u was already a mature process; the leading edge process was 0.6u.

The 4th generation x86 processor was first introduced in April 1989.  While the instruction set is similar to the 386 with addition of only six new instructions, it integrates on-chip the floating number processor and unified L1 cache.  i486DX2 has 8KB write-through cache. The processor runs at 66MHz and the front side bus is at half speed of 33MHz.  While software compatible with 386, the processor bus is not.  Intel literature said i486 featured a 32-bit RISC-technology core despite of x86 carrying CISC baggage; so by then it is clear RISC is preferred computer architecture.

i486DX2 comes in 17x17 168-pin 0.1" pitch PGA ceramic package, which was quite common for that era.  The PGA packaging would continue except for Pentium II which used the slot package.  Eventually, land grid array, LGA, a surface mount technology would become the standard.  Throughout ZIF sockets are used to house the CPUs.  The maximum power for i486DX2 is about 6W.  The junction-ambient thermal resistance is 17 deg/W.  A heat sink with forced air flow would be required to operate at room temperature. 

Twenty years later, the transistor count is increased by three orders of magnitude, the clock frequency by a factor of 50, the power consumption by 20, the pin count by 10 and the core voltage dropped by 5.

i486 features a five-stage pipeline, so many instructions execute in one clock cycle.  The design goal was to have 2 to 3 times performance improvement over 386 at the same clock with 4 times the transistor budget.  Intel made extensive use of CAD tools developed in cooperation with UC Berkeley.   Intel created its own hardware description language, iHDL, which was not replaced by Verilog until 2005.  Standard cell library was created to enable automatic RTL to layout conversion.  It was first time RTL to layout system ever employed in a major microprocessor development program, though it is only applied to the control logic.  Data path was still done manually.  It is interesting to note that Intel had been using transparent latches with a two-phase clocking system, which was not compatible with synthesis tools.  By the time of Pentium design, the two-phase clocking scheme was largely replaced by a single-clock and master-slave flip-flops. [Gelsinger, "Coping with the Complexity of Microprocessor Design at Intel –  A CAD History"]

The main enhancement of 486 over the previous generation is the inclusion of 8KB on-chip cache, which is a buffered write-through four-way set-associative with LRU replacement 16-byte line size. [Crawford, "The i486 CPU: Executing Instructions in One Clock Cycle", Feb. 1990]  About a quarter of the die area is occupied by the cache.  Today's core would have 32KB data and 32KB instruction L1 cache and an internal unified L2 cache of 256KB and multicore processor could have more than 20MB L3 cache shared by all cores on chip.  The L1 instruction cache is 4-way associative and the data cache 8-way associative; the L2 cache is 8-way associative and the L3 cache 16-way associative.  And the cache would take up majority of the die area.

i486DX2 has 32-bit address lines with byte enable signals, 32-bit data lines with parity, write/read memory and I/O control, bus control, bus arbitration, burst control, cache control signals.  Out of the 168 pins, 24 are Vcc and 28 are Vss.  JTAG boundary scan ports are included.  The CLK input has a maximum frequency of 33MHz.  The logic input level is TTL compatible, i.e. 2.0V and above as high.  The minimum setup time is 5ns, and hold time 3ns.