80486 PC: Motherboard

Motherboard

 

This motherboard has 8 ISA bus expansion slots, 3 of them with VESA local bus, 2 of them 8 bit.  The ISA bus dates back to the first PC, the 8-bit PC XT bus.  It was extended to 16-bit with PC AT.  The increasing resolution of the display demanded a fast bus, so a simply VESA local bus was added mainly to support graphics card.  By 1994, PCI bus was starting to appear in the motherboard.  Even so the graphics card still demanded more bandwidth, so the AGP slot was introduced.  Eventually, PCI Express serial bus becomes the only expansion bus remaining.  The Universal Serial Bus would not appear for another one or two years and it took a few more years to be prevalent.

The CPU socket is a 19x19 238 pin ZIF socket.  It can house a number of 486 models.  However, it is not keyed for i486DX2, so installation requires care to note the chip orientation.

The main crystal is 14.31818MHz, being multiple of 4.77MHz, the CPU frequency of PC XT and multiple of 3.58MHz, the frequency of NTSC color burst signal.  The CPU frequency generator chip AV9107-03 generates a 33.3MHz clock for the CPU bus.  The ISA bus frequency is usually set at around 8MHz; so the configurable divider is set to 4 on this board.

The OPTi 82C895 chipset is the most complex IC besides the CPU.  It handles the cache, DRAM, VESA and ISA interfaces.  It uses 0.8um CMOS and comes in 0.5mm pitch 208-pin plastic quad flat pack.   Its companion chip 82C602 is a buffer device for AT bus signals with addition of the real-time clock function.  It is fabed with 1.0um CMOS and packaged with 100-pin plastic flat pack.  OPTi Inc was a major chipset producer in the early 1990s, its stock hit peak in 1995, but the company faltered soon afterwards because of the dominance of Intel in the chipset market.

The motherboard has 9 x 32KB 15ns SRAM chips that are used as L2 cache, for a total of 256KB with tag.  Interestingly the size of L2 cache stays the same in the latest Intel processors.  The board sockets can accommodate 4 x128KB and one 32KB for total 512KB.  The SRAM is asynchronous; there is no clock.  In the read cycle, 15ns after the address lines are presented, data lines are valid; in the write cycle, assert address, write enable and data for 15ns, the data are written.  The SRAM is power hungry; each chip consumes 150mA during operation.  The cache controller in the chipset uses the direct-mapped write-back cache organization.  The cache line size is 16 bytes.  The 8-bit tag is stored in one 32KB SRAM, so the total cacheable memory is 64MB.  The cache memory shared the 32-bit bus with the CPU.  When there is an L1 cache miss, the lower address bits A[17:4]  are used to read the tag SRAM and the content is compared with the upper address bit A[25:18].  If there is a match, the SRAM read or write for the next four bus cycles; otherwise the main memory is accessed.  When the CPU clock period is 30ns, the SRAM is fast enough to support the cache timing  2-1-1-1, i.e. first word taking two cycles and the one cycle for each of the remaining three.  If the write-back mode is enabled, one of the tag bits is the dirty bit and the cacheable memory size is halved.  When the data is written to the cache, the main memory is not accessed to improve efficiency, but the memory is inconsistent so the dirty bit is set.  The next time, when there is cache read miss, the cache must first be flushed to the main memory then the CPU and cache read the new data concurrently from the main memory.  If it is a write miss, the cache is bypassed.

The main memory are in 4 72-pin SIMM slots.  In 1994, DRAM was still expensive, but soon its price would drop and SIMM would be replaced by DIMM.  Though SIMM has contacts on both sides, they are connected together.  I believe it had 2 4MB modules and I added another 4MB a little later at considerable expense.  Each of the three modules uses 8 TI's 4M-bit fast page DRAM.  Two modules have 60ns RAS access time, and the other 70ns.  Afterwards, in 1996, the DRAM price dropped significant and I added another 4MB module that uses 2 16M-bit DRAM from LG also 70ns access time.  In 1998, TI sold its memory business to Micron.  The board can have up to 128MB.  The 72-pin SIMM is a standard defined by JEDEC.  It has 36 data lines and 14 address lines; with enable lines, it can support up to 2GB per module. 

There are presence detect bits that indicate the speed and size of the memory.   The DRAM access is more complex.  The DRAM used here is asynchronous.  Take the TI TMS44400 for example, it has 10 address lines, 4 data lines, write enable, output enable, column address strobe (CAS) and row address strobe (RAS).  The memory is organized into a matrix.   In the read cycle, the row address is driven along with the falling edge of RAS, then the column address is driven with the falling edge of CAS and some time later the data is available.  The 60ns access time refers to the time from the falling edge of RAS to data available.  A precharge time is required before next read, so the total cycle time is 110ns.   When reading on the same row address, the access can be faster using the page mode by keeping RAS and strobing only CAS for different column addresses.   One page is 1024 columns.  The minimum page-mode cycle time is 40ns.  Consider the case that a cache line needs to be filled, so 4 reads take 230ns or 8 clock cycles at 33MHz while a cache access is only 5 clock cycles.  The DRAM also requires periodic refresh; the refresh time is every 16ms.  A refresh is achieved by strobing each of 1024 rows.  The power consumption for each chip is about 100mA, so more than 20 times less per bit than the SRAM.

This motherboard has a regulate DIN connector for keyboard.  Mini DIN connectors would becomes standard for keyboard and mouse.  The keyboard controller chip is made by American Megatrends.  There is no mouse port, which has to come in on a expansion card as well as the printer port and the serial ports.  There is also no interface for floppy, CD and hard drive.  They also have to come from an expansion card.

The BIOS is from American Megatrends, a company specialized in PC BIOS and survived to today.  The version of BIOS for this motherboard is 486DX ISA BIOS 1993.  It is in a 28-pin DIP 64KB UV erasable EPROM with 45ns access time, 16-bit address and 8-bit data.  The motherboard socket can accommodate a 32-pin DIP.

The motherboard is a product from Taiwan, which dominated PC motherboard production and spurred a lot of entrepreneurs that sold PC in local stores.  At the time, through-hole technology was still fairly dominant.  All the discrete components are through-hole.  They belong to the era when the clock and the edge rate are slow.  Nowadays, the lead inductance on the through-hole capacitors would make them useless as bypass.  The number of bypass capacitors for the CPU is far fewer than in today's CPUs which requires multiple rails.  A lot of 74 TTL logic chips in DIP are still used here: F series for the fast logic and LS for the slower logic.  Most of these chips were made by National Semiconductor, which Fairchild Semiconductor was a part of.  Motorola also made a few of the logic chips; Motorola spin off On Semiconductor continued this part of the business. The PC board is dated the 21st week of 1994 and I bought it in the summer of that year.  Most of the components are also made in 1994 and a few in 1993.  The technology was rapidly evolving, so everything was fairly fresh.  The PC dimension is 10.2" x 8.65" (26cm x 22cmm)  and the standard 62mil thickness.  This is smaller than the 13" x 8.5" Baby AT form factor.  Later the ATX form factor, 12" × 9.6" would become the standard for desktop PCs.  The PC board has probably 4 layers: the top and bottom are signals routed in orthogonal directions and the inner two are Vcc and GND planes.  

The board itself runs on a single 5V, but +/-12V and -5V are brought in and distributed to the ISA bus expansion slots.  The 12-pin power connector pin-outs are Power Good, +5V, +12V, -12V, Ground, Ground, Ground, Ground, -5V, +5V, +5V, +5V.   This pin assignment goes back to IBM PC XT.  Eventually 3.3V is also brought in from power supply and -5V is dropped.  This board has options to install a low-drop-out voltage regulator to generate supply voltage for a 3.3V CPU.  More and more voltages had to be generated on board to accommodate multiple rails and continuing dropping core voltages with peak current reaching over hundred amps.