Howland Current Source Impedance

 Here we derive the source impedance of the Howland current pump.  The ideal current source impedance is infinity.  The Howland current pump is depended on resistor matching.  We consider the effect of mismatch on the source impedance.

The source impedance is R3/mismatch, a result is given in AoE3, which appears to err on which resistor R3 refers to.

Assume the resistors are 0.1%.  The worst case source impedance is 250 times of  R3 in the diagram.  For small current on the order of 1mA, R3 is on the order of 5KOhms, the source impedance is about 1MOhms worst case, compared with LT3092, which has an output impedance of 100MOhms at 1mA and 2MOhms at 10mA.  

In the so-called "improved" Howland current source, a buffer is inserted to have a separate resistor to set the current.  We can similarly derive the output impedance.

If we assume R1=R2=R3=R4=Rs, the output impedance is Rs/(2*tol), which is twice as large as before.

A Current Source Circuit

 As an application example, the data sheet of a shunt voltage reference presents an 1mA precision current source as shown here, 

Normally, the negative feedback forces the input terminals of the opamp to be the same voltage and the output applies 2.5V across 2.49K to generate 1mA current to the load.

 However, it is possible for this circuit to get stuck at the 0V.   Note that the negative rail of the opamp is at the ground in the single supply configuration.  With both opamp inputs at 0V, the offset voltage of the opamp causes the output to go to ground.  This is a stable operating point if the offset voltage and the gain are in the right range.

If the opamp's negative rail is a negative voltage, the output saturates at the negative rail, the negative input is clamped at one diode above and the positive input would be more positive (except for certain loads) which would force the opamp out of saturation.

Is there a way to keep the circuit from settling in this undesirable operating point?  One way is to inject some voltage on the opamp's positive input (diode blocking it after it is unstuck).  The voltage divider can be adjust to minimize the error current.  But invariably an error current (a few microamps)  would go into the load if it has to operate over temperatures and a wide range of loads.

NAND and NOR Flash

 The two types of flash memory devices, NAND and NOR, are familiar to people in tech.  Most people understand the difference between the two: the NAND flash memory is like a hard drive disc that is accessed sequentially and the NOR flash memory can be read randomly and is used for code execution.  Some are even aware that the NAND flash gets its name from the NAND gate and the NOR flash from the NOR gate.  Beyond that how exactly these flash memory devices work can be a little fuzzy.

Fundamentally, both types of Flash memory devices work under the same principle.  Each memory cell has an isolated floating gate to storage charges, which are programmed or erased by the hot-carrier injection and the quantum tunneling process.  The presence or the absence of charges on the floating gate changes the threshold of the transistor.  The difference lies how the cells are organized to achieve the desired the features.  Also the flash memory is erased one sector at a time while the EEPROM is erased one byte at a time.

We start with the NOR flash.  A cell is read by applying voltage to the WORDLINE, connected to the control gates of a row of transistors, from the row address decoder logic.  If the cell is written, the floating gate has negative charge and the device threshold is higher, so the channel connected to the source has higher resistance than the erased cell.  This difference can be sensed with a comparator.  Note the source of every memory cell has a connection the SOURCE node. To program a cell, a higher voltage (like 12V) is applied to the gate of the cell and a voltage (like 5V) is also applied to the drain.  The electrons flows onto the floating gate by the process of hot carrier injection, which the electrons gain enough kinetic energy from the strong electric field to overcome the bandgap of SiO2.  The cells in a sector are erased at the same time by applying a high voltage to the body well and the word lines grounded and the drain is left floating, so the electrons are removed from the floating gate through a quantum tunneling process.

The NAND flash has fewer connections.  Each memory cell only connects to the adjacent cell.  So the cells are packed more densely.  Now the question is how to read out individual cells.  The particular cell to be read has to pass information through other cells.  The key is to apply a high voltage to other cells so they act as passing transistors regardless the state of those cells.  The passing voltage is lower than the programming voltage, so the cells are not altered.  For the NAND flash, both programming and erasing are done with tunneling.  During the programming the NAND flash cell, the bit line is grounded and the source selector is turned off.

Now the question is why they are called NOR and NAND flash respectively.  If we look at the NOR and NAND gate, we only see a little superficial resemblance.  

The NOR and NAND labels do make a quick distinction of the two types of flash although the inner working has little to do with these logic gates.

The description here provides perhaps a sufficient understanding for some, while others might be curious about the details of the programming and erasing process in the device level, which we hope to explore later.

USB -C Hub HDMI Failure

 VAVA 7-in-1 USB C hub VA-UC017,  3x USB 3.0 5Gbps USB A ports, SD/uSD card slots, HDMI, PD charging port 100W max.  $25, 100x40x13mm, 60g (31g w/o casing). It worked well with both PC and Android phone for about 3 years before the HDMI stopped working; other functions still seem to work.

We will try a teardown and see if we can identify the problem.  

Opening up was a little difficult.  The casing is one piece aluminum with both ends plastic; one end is the USB C cable and the other end is the HDMI connector.  The plastic is secured to the casing with epoxy; we had to pry open the USB C side. 

The PCB appears to have a date code of 2021-01-11 and the assembly time is maybe 21-03, consistent with time purchase time of 21-05.    The USB C cable wires are hand soldered to the PCB and the soldering work is rather poor, but the connections appear intact.  The USB C wires seem OK: the USB 3 signal pairs are individually shielded and power wires are large gauge.  Overall, the component assembly seems good; I did notice a few solder balls, but overall the PCB is clean.  Also note the conductive foam on top of the HDMI connector and SD/uSD card slots.  The aluminum casing is anodized; the areas contacting the conductive foam are exposed.

VL815-Q7 by VIA Labs is a USB 3.1 Gen1 4-port hub controller. VIA's VL102-Q4 is a DisplayPort Alternate mode and Power Delivery 3.0 controller for USB-C devices.   DP Alt Mode allows the transmission of DisplayPort signals over USB-C connector.   ITE Tech IT6563FN is a 4-lane DisplayPort 1.2 to HDMI 2.0 converter.  MA8121N is a USB 2.0 SD/MMC card reader controller, by Prolific Technology or possibly a Chinese clone.  Puya P25Q40H is a 4Mb SPI serial Flash.  SM4307 is a P-channel power MOSFET by Sinopower.   There are three switching regulator ICs, maybe one or more LDOs,  Two of switching regulators are likely M3Tek's MT3121NSBR, 5V Input 1.5A/2A(Peak) 2.5MHz Synchronous Step-Down Converter. There are a number of SOT-23 components, which are either transistors or LDOs.

The HDMI connector does not appear to be well soldered; there is no solder above the holes.  Also interesting a number of components on the HDMI signals are not populated; they could be ESD protection devices, or filters, like TI's ESD224, or STMicro's ECMF4-2450A60N10 (ESD and common-mode filter),  which the footprints seem to match.  

I reflowed all the HDMI connector pins, but the HDMI still does not work.  It'll require a more in-depth troubleshooting, which we try in the future.

Bandgap Reference

Does the bandgap reference really have anything to do with the silicon bandgap voltage?

The basic idea of the bandgap reference is to obtain a low temperature coefficient voltage source by cancelling the negative temperature coefficient of the diode forward voltage with the positive temperature coefficient of differential $V_{be}$.   The difference of the $V_{be}$ of two different size but otherwise identical bipolar transistors is $\Delta V_{be} = k T /q \ln \eta$ (PTAT), where $\eta$ is the current density ratio, $k=1.38\times 10^{-23}, q=1.6 \times 10^{-19}$.  The diode voltage tempco is about -2mV/°C; to match that, $k/q \ln \eta$ = 2m, so $\Delta V_{be}$ = 600mV at the room temp.  And the diode voltage at the room temp is also about 600mV.  So the output is about 1.2V, which they say is close to the silicon bandgap voltage (1.166V at 0K).  But the essential scheme does not really seem to depend on it.

Update:

Recently I watched a lecture by A. Paul Brokaw,  "A Transistor Voltage Reference, and What the Band-Gap Has To Do With It", 1989.  He gave the clearest explanation that I've ever seen.  PTAT ($\Delta V_{be}$) and CTAT ($V_{be}$) with the right proportion add up to the constant reference, and at 0K, PTAT is 0V and $V_{be}$ is equal to the bandgap voltage.

VG0 is the silicon bandgap voltage, Vbeo is the base-emitter voltage at temperature To. 

Logarithmic Amplifier Compensation

A logarithmic amplifier is based on the exponential relationship between the collector current and the base-emitter voltage.  It is also an opamp circuit that has a gain in the feedback path, so a unit-gain stable opamp may not be stable.  It is necessary to add phase compensation.

Here is the simple logarithmic amplifier circuit and we derive the loop gain,

We will use OP-41 as the opamp. OP-41 has a typical DC gain of 134dB and gain-bandwidth product of 500K (ω1 = 3e6).  That puts the dominant pole at about 0.1Hz.  A high order pole above 1MHz leads to a phase margin of about 77 degrees.  This is typical of an internal dominant pole compensated opamp.  As we can see the loop gain plot is shifted up, the phase margin is reduced.

We place a capacitor across the collector and the emitter as compensation.  The capacitor adds a lag network.

With the zero a decade below the cross over frequency (Rs C > 3us), this results in an improved phase margin (back to near the unit-gain phase margin).

We have ignored the junction capacitance from the npn transistor.

We compare these with simulations.  We model the opamp as a two-pole transfer function.  The input current is 1mA.  The feed back has a gain of 40 or 32dB.

The phase margin is 8° without compensation and 50° with a 22n cap.  The zero and the pole are at the estimated location of 7.2KHz and 280KHz.

Other compensation methods are adding an emitter resistor to reduce the feedback gain and a lag network at the input, which is necessary in the case of a current source input when the emitter resistor would be too large.  

Note that the output resistance of the transistor has to be included to get the correct pole frequency.

The compensation can be improved, which we will discuss in a later time.

Pen Drawing Tablet

XP-Pen Star G640 drawing tablet, 6x4", 8192 pressure levels, battery free stylus with two push buttons, resolution of 5080 LPI, for $25

It works on the electromagnetic induction principle.  

From the teardowns that other people have shown on the internet, the stylus is entirely passive with a coil and capacitors, that would exclude any encoding scheme.  The working hypothesis is that the tablet will transmit a signal to excite the LC tank, the LC tank oscillates and signals get picked up by the tablet.  The working area of the tablet is a PCB with horizontal and vertical traces.  The position of the stylus is calculated perhaps by centroiding on the signal strength.

The pressure level is transmitted probably by frequency modulation.  There is a ferrite on the rod that the nib is attached and the rod is pushed on a spring.  The pressure on the nib moves the ferrite relative to the coil, changing the resonant frequency.  And pressing the button connects additional capacitor to the tank, also altering the frequency.

We will try to verify the working principle without disassembling the stylus or the tablet.  We will use a simple wire loop to pick up the signals.

Without the stylus on the tablet, we pick up some signal from the tablet.   It is possibly just a 500KHz square wave ac-coupled.

 When the pen is on the tablet, we see the oscillating LC signal. 

We can take a close look at the frequency of the oscillation,

Zooming in at the peak, we can see the difference in the rising envelop when the tablet is driving and the falling envelop when the stylus is free oscillating.

At pressure level 0, the frequency is about 506KHz, and at the max pressure of 8192, the frequency is about 530KHz.  So the circuitry has a resolution of 3Hz.  When the upper button is pressed, the frequency is 484KHz, and the lower button 464KHz.  And the frequency changes from there if pressure is applied while the button is pressed.

We can make a circuit model and run simulation to compare with the measurements.

We will design a frequency to voltage conversion circuit to extract the pressure level in a future blog.

The stylus is detected with the tip about 1cm above the tablet; there is some hysteresis on that distance.  Placing the stylus flat lengthwise on the tablet  does not work, but vertically flat widthwise works.  This is a little curious; perhaps the excitation is only generate by traces in one direction.  It may be a deliberate design choice, because the stylus can be left on the tablet without affecting other pointing devices.

When we place a ferrite toroid around the stylus, the tablet can register button clicks with buttons being click.  This implies that the presence of the ferrite toroid lowers the resonant frequency to be in the range of that of button click.