The two types of flash memory devices, NAND and NOR, are familiar to people in tech. Most people understand the difference between the two: the NAND flash memory is like a hard drive disc that is accessed sequentially and the NOR flash memory can be read randomly and is used for code execution. Some are even aware that the NAND flash gets its name from the NAND gate and the NOR flash from the NOR gate. Beyond that how exactly these flash memory devices work can be a little fuzzy.
Fundamentally, both types of Flash memory devices work under the same principle. Each memory cell has an isolated floating gate to storage charges, which are programmed or erased by the hot-carrier injection and the quantum tunneling process. The presence or the absence of charges on the floating gate changes the threshold of the transistor. The difference lies how the cells are organized to achieve the desired the features. Also the flash memory is erased one sector at a time while the EEPROM is erased one byte at a time.
We start with the NOR flash. A cell is read by applying voltage to the WORDLINE, connected to the control gates of a row of transistors, from the row address decoder logic. If the cell is written, the floating gate has negative charge and the device threshold is higher, so the channel connected to the source has higher resistance than the erased cell. This difference can be sensed with a comparator. Note the source of every memory cell has a connection the SOURCE node. To program a cell, a higher voltage (like 12V) is applied to the gate of the cell and a voltage (like 5V) is also applied to the drain. The electrons flows onto the floating gate by the process of hot carrier injection, which the electrons gain enough kinetic energy from the strong electric field to overcome the bandgap of SiO2. The cells in a sector are erased at the same time by applying a high voltage to the body well and the word lines grounded and the drain is left floating, so the electrons are removed from the floating gate through a quantum tunneling process.
The NAND flash has fewer connections. Each memory cell only connects to the adjacent cell. So the cells are packed more densely. Now the question is how to read out individual cells. The particular cell to be read has to pass information through other cells. The key is to apply a high voltage to other cells so they act as passing transistors regardless the state of those cells. The passing voltage is lower than the programming voltage, so the cells are not altered. For the NAND flash, both programming and erasing are done with tunneling. During the programming the NAND flash cell, the bit line is grounded and the source selector is turned off.
Now the question is why they are called NOR and NAND flash respectively. If we look at the NOR and NAND gate, we only see a little superficial resemblance.
The NOR and NAND labels do make a quick distinction of the two types of flash although the inner working has little to do with these logic gates.
The description here provides perhaps a sufficient understanding for some, while others might be curious about the details of the programming and erasing process in the device level, which we hope to explore later.
