PCB Layout: Basics

PCB layout generally is not a task that many EE's are proficient at. They may even consider it somewhat beneath them and it is the work for technicians. Many schools do not consider it significant enough to warrant a course and EE students are expected to pick it up by themselves when needed. But actually PCB layout concerns a wide range of topics, including material science, electrical engineering, mechanical engineering, thermal engineering, packaging technology, fabrication technology, assembly etc. A good layout engineer must be aware of concepts in all these areas.

Let's start with printed circuit board materials. The basic conducting material is copper, an excellent conductor of both electricity and heat. The thickness of copper is given in ounce, the weight of one square foot; one ounce and two ounces are common.  The thickness of 1oz copper is given as 1.37mil.  (The copper density is 8.96g/cm³, so 1.37mil is 1.02oz.) Exposed copper traces are usually coated with very thin layer of tin or nickel (~0.1mil) for preventing oxidation. Outer layers and via are plated with copper. Electrical resistivity with temperature coefficient and thermal conductivity are relevant to PC layout. Plated copper has higher resistivity than copper sheet. The most common PCB dielectric is FR4, others include G10, polyimide. Dielectric constant with frequency variation and loss tangent are needed for layout. The temperature range where the dielectric is stable is also important. Polyimide has higher temperature range than FR4, so it is used in space electronics. PC boards are built in layers with core and prepreg. Prepreg bonds core laminates under pressure and temperature. Board is covered with solder mask except for pads or other exposed areas.  The solder mask gives the PCB the common green color, but the other colors are also available, such as blue, maroon and white.  Silkscreen is used for component labels.

From electrical point view, PCB traces establish electrical connectivities, but they add resistance, inductance and capacitance. Resistance causes joule heating and voltage drops. Especially for high current traces, trace width must be sized correctly. Charts are given in current vs trace width for different temperature rise. Note that outer layer traces can carry much larger current for the same temperature rise. Trace inductance and capacitance are more important in high speed designs, where they may significantly impact signal integrity. Electromagnetism which has been simplified to Kirchoff laws in circuit design now manifest itself in its full form. The spatial arrangement becomes important. EM compliance has to be dealt with in layout. Transmission line effect has to be taken into account. 2D and 3D field solvers are becoming more routinely employed to determine signal integrity in high speed applications.

PCB is after all a mechanical structure. It has to be mechanically mounted to other structures. Design files convey mechanical information. Some terminologies come from mechanical engineering.
PCB is also a medium for heat to conduct. Thermal analysis of circuit board depend on the layout. Layers can be added for thermal purpose, copper area can be created to reduce thermal resistance.
Circuit elements come in various of packages. A layout engineer must keep abreast of advances in packaging technologies.

PCB layout is bounded by the capabilities of fabrication technologies and cost. A layout engineer must be aware of constraints placed by these capabilities and aim for reliable manufacturing. 7 mil minimum trace width and spacing are fairly routine.

During actual layout, component placement is the most important for it eventually determines the qualities of layout.  A proper partition of the circuit section is guided by the foremost by the current flow.  The loop area must be minimized.  High current circuit sections should be close to the voltage source and away from the sensitive circuits.

Layout is prone to human errors. Long gone are the days when layout is done manually with tape. A good layout software is essential.

Continued here.

EEssential Weekly Notes #4

Bond wires

The standard bondwire is 1mil in diameter and 2mm in length.  It has very roughly 1nH/mm. [T. Lee, CMOS RF]  A D-PAK MOSFET (AOD452) has 6.5mOhms Rds on with 2x12mils wire bond; the wire resistance is ~0.6mOhm.  [Alpha & Omega, AN911].   The package resistance is about 20% of total MOSFET resistance. For DPAK, the package resistance is 0.5mOhm with Powerbond II [Infineon, PowerBond]. 

Flex circuits

For Minco, 16 layers max, 1.5mil min trace/space, 2mil min hole diameter, 6mil thick per layer.

Solder Conductivity

The 63% tin 37% lead solder alloy electric resistivity is 144e-9 Ohm-m, thermal conductivity 40.9 W/m-K, and thermal expansion coefficient 21.4e-6/C. As a comparison, the copper resistivity is 17e-9 Ohm-m. So the solder has more than eight times the resistance. Plugging a via hole with solder would do very little to reduce its resistance.