Logarithmic Amplifier Compensation

A logarithmic amplifier is based on the exponential relationship between the collector current and the base-emitter voltage.  It is also an opamp circuit that has a gain in the feedback path, so a unit-gain stable opamp may not be stable.  It is necessary to add phase compensation.

Here is the simple logarithmic amplifier circuit and we derive the loop gain,

We will use OP-41 as the opamp. OP-41 has a typical DC gain of 134dB and gain-bandwidth product of 500K (ω1 = 3e6).  That puts the dominant pole at about 0.1Hz.  A high order pole above 1MHz leads to a phase margin of about 77 degrees.  This is typical of an internal dominant pole compensated opamp.  As we can see the loop gain plot is shifted up, the phase margin is reduced.

We place a capacitor across the collector and the emitter as compensation.  The capacitor adds a lag network.

With the zero a decade below the cross over frequency (Rs C > 3us), this results in an improved phase margin (back to near the unit-gain phase margin).

We have ignored the junction capacitance from the npn transistor.

We compare these with simulations.  We model the opamp as a two-pole transfer function.  The input current is 1mA.  The feed back has a gain of 40 or 32dB.

The phase margin is 8° without compensation and 50° with a 22n cap.  The zero and the pole are at the estimated location of 7.2KHz and 280KHz.

The compensation can be improved, which we will discuss in a later time.